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Abstract: |
This paper proposes a circuit structure which can be used for both synchronous and asynchronous pipeline control. It is a self-circulation structure with embedded delay network, and a pipeline can be controlled by this structure with the interconnection of adjacent stages. This paper first proposes a basic circuit structure, then a linear pipeline is designed with self-circulation structure. The performance of linear pipeline is analyzed, and a 16-bit digital signal processor (DSP) with the structure is designed to prove the validity of the structure. Results show that about 10%-15% power consumption is saved with self-circulation structure compared with synchronous counterpart, while almost the same performance is achieved. |
Key words: pipeline self-circulation timing analysis asynchronous circuit |
DOI:10.11916/j.issn.1005-9113.2009.06.007 |
Clc Number:TP273 |
Fund: |