| Author Name | Affiliation | | ZHU Ming | Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China
National Key Laboratory of Science and Technology on Reliability Physics and Application Technology of Electrical Component,Guangzhou 510610,China | | XIAO Li-yi | Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China | | TIAN Huan | Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China |
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| Abstract: |
| This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes. |
| Key words: memory multiple bit upsets improved hamming codes two-dimensional error codes |
| DOI：10.11916/j.issn.1005-9113.2010.05.024 |
| Clc Number:TN402 |
| Fund: |
