| Author Name | Affiliation | | Bin Zhou | Research Center of Basic Space Science, Harbin Institute of Technology, Harbin 150001, China | | Mingxue Huo | Research Center of Basic Space Science, Harbin Institute of Technology, Harbin 150001, China
Dept.of Microelectronics Science and Technology, Harbin Institute of Technology, Harbin 150001, China | | Xinchun Wu | School of Information Science and Technology, Southwest Jiaotong University, Chengdu 610031, China |
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| Abstract: |
| A novel BIST scheme for reducing the test storage (TS) is presented. The proposed approach relies on a two-dimensional compression scheme, which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters (RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the width of the test set, and conclude that the probability of encoding a n-bit test cube with s specified bits using a (smax+1+20/n)-stage LFSR with a fixed polynomial is 1-10-6. Experimental results for the ISCAS’89 benchmark circuits show that compared with the previous schemes, the proposed scheme based on LFSR-RC reseeding requires 57％ less TS and 99.1％ test application time (TAT) with simple and uniform BIST control logic. |
| Key words: built-in self-test linear feedback shift register (LFSR) ring counters(RCs) test compression |
| DOI：10.11916/j.issn.1005-9113.2015.03.008 |
| Clc Number:TN47 |
| Fund: |
