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| Abstract: |
| With a reduction in transistor dimensions to the nanoscale regime of 45 nm or less, quantum mechanical effects begin to reveal themselves and have an impact on key device performance parameters. As a result, in order to develop simulation tools that can be used for the design of nanoscale transistors in the future, new theories and modelling methodologies must be developed that properly and effectively capture the physics of quantum transport. An artificial neural network (ANN) is used in this paper to examine nanoscale CMOS circuits and predict the performance parameters of CMOS-based digital inverters for a temperature range of 300 K to 400 K. The training algorithm included three hidden layers with sizes of 20, 10, and 8, as well as a function fitting ANN with Bayesian Backpropagation Regularization. Further, simulation through HSPICE using Predictive Technology Model (PTM) nominal parameters has been done to compare with ANN (trained using an analytical model) results. The obtained results lie within the acceptable range of 1%-10%. Moreover, it has also been demonstrated that the ANN simulation provides a speed improvement of around 85 over the HSPICE simulation, and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits. |
| Key words: optimization ultradeep submicron technology unified MOSFET model artificial neural network |
| DOI：10.11916/j.issn.1005-9113.2022029 |
| Clc Number:TP183,TN710 |
| Fund: |
