To improve the performance of AES on FPGA, an idea of fully pipeline is proposed. After analyzing the needs of memory and logic elements deeply and finding out the factors restricting the efficiency of data blocks, the high-speed operation of the pipeline node model with dual channel mold is found to implement the AES full line. Experimental results show that the throughput of the AES encryption and decryption algorithm on FPGA of EP4CE40F29C8, can reach up to 7.2 Gbps. In the framework of fully pipeline, the idea of dual channel mold makes all the pipeline data blocks in efficient working condition. System under the premise of low-cost achieves a substantial improvement in performance. 