Because the FPGA factories presently do not offer the special testing function in their EDA tools, this paper addresses the design of a navigated mapping method used for FPGA testing. The navigated mapping tool totally controls the basic elements and exactly controls the usage of FPGA logic resource, tests some targetable logic of the FPGA and increases the coverage of each test vector effectively, implements the FPGA software defect-tolerance function. The result is well proven in test converage through 128 test cases.