For the good performance of DRM／DAB／AM／FM frequency synthesizer, the implementation of a high-speed large division ratio low-power pulse swallow frequency divider is described, which consists of a divided-by-32／33 dual-modulus prescaler (DMP), a 5 bits swallow counter, an 11-bits programmable divider, and a time sequence control circuit. The different modules of pulse swallow frequency divider apply SCL, TSPC, CMOS static flip-flop DFF, and CMOS static flip-flop DFF with preset to realize the low power, large division ratio, and high speed performances. The chip has been fabricated in a 0.18 μm CMOS process of SMIC and the core area is 270 μm×110 μm. Measured results show that its most high operation frequency is 3.4 GHz and the rang of operation frequency is from 0.9 GHz to 3.4 GHz. And when the operating frequency is 3.4 GHz and division ratio is 45 695, the maximum core power consumption is 3.2 mW under 1.8 V power supply. Its performance satisfies the requirement of DRM／DAB／AM／FM frequency synthesizer.