To reduce the phase noise of fractional-N phase locked loops (PLLs) and suppress the output spurs of PLLs caused by doubling the frequency of reference clock with traditional exclusive-OR gates (XOR), a low-spur reference frequency doubler (RFD) with a hybrid duty cycle calibration loop (DCCL) was proposed. The RFD doubles the frequency of input clock and outputs the reference clock to the PLL, effectively suppressing the phase noise of the PLL by reducing the divide ratio. To reduce the frequency jitter of the reference clock and the output spurs of the PLL caused by the duty cycle deviation of the input clock, the RFD first roughly calibrates the duty cycle with a digital-controlled edge adjustor and then improves the precision with an analog DCCL. The two methods work collaboratively based on the proposed controlling algorithm, achieving a wider calibration range and a higher precision simultaneously. Simulation results show that the proposed RFD could reduce the duty cycle error of a 100 MHz input clock from 13.8% to 0.007%, and decrease the output frequency error to 380×10^-6. The circuit was fabricated in a 40 nm CMOS process. Test results show that it could suppress the in-band phase noise by 6.67 dB and quantization noise by 5.61 dB, and after the duty cycle calibration, the spurs at 1/2 reference frequency offset in the output signal spectrum of the PLL were reduced by 9.52 dB. The in-band noise and quantization noise of PLLs could be reduced by doubling the frequency of the reference clock of PLLs. The spurs in the output signal spectrum of PLLs could be suppressed efficiently by calibrating the input duty cycle of the RFD.