FPGA has fixed number of I／O or CLB, which resulting in a limitation to the implementation of a very large complex system in a single FPGA. This paper addresses a partitioning method used for a multi-FPGA system implementation with partly guidance of User Constraint File and FPGA EDA flow. The partitioning method can improve the partitioning efficiency, and reduce the complexity of a multi-FPGA system design. Based on the proposed method and the multi-FPGA system architecture, a partitioning tool was implemented, which has the capability of designing a nine-chip multi-FPGA system.