In order to obtain low power consumption and high fault coverage, a new single-double input change deterministic test pattern generator is presented based on a single input change technology and 2-bit twisted ring counter. Firstly, unlike traditional deterministic test schemes storing the deterministic seeds, the presented scheme saves the control signal bits in ROM. With these bits, the deterministic seeds and patterns are generated by single-double input change. It is beneficial for power consumption and area overhead because the length of control signal bits are just about 1/2 of deterministic seed's. Secondly, 2-bit down counter can reasonably filter redundant vector, and it greatly shorten test time and reduce overall energy consumption. At last, considering different needs, the test pattern compression algorithm and three kinds of x assignment algorithm are proposed. Experimental results show that the average power reductions are up to 42.36%, 32.32%, 38.94%, and the test length reductions are up to 77.6%, 86.1%, 84.3%, and then the test data storages are decreased by 79.4%, 65.2%, 68.1%, respectively.