A distributed fetch structure of M5-edge is designed for the purpose of expanding the design space of EDGE architecture. The structure includes the overall function, distributed fetch unit and the interconnection network between the units. Two kinds of fetching block head are realized, including fixed fashion and round robin one. The analyses, which are made in different distributed fetch unit counts, provide the leave of reduction of distributed fetch comparing with the ideal lumped fetch model, as well as the difference between the two fashions of fetching block head. Furthermore, the effect of the processor performance by the communication latency and the cache miss rate are shown.