Delay lock loop (DLL) supported 90°phase shifters are widely used in double data rate synchronous dynamic random access memory (DDR SDRAM) to generate 90°phase-shifted clock, which achieves double data rate sampling and improves data-rate. Digitally controlled delay line (DCDL) plays a critical role in the DLL supported 90°phase shifter. To remove glitches in traditional DCDL during the process of delay adjustment, the causes of glitches generation were analyzed, and a glitch free digitally controlled delay line (GFDL) with latch and clock gating was proposed. The latch and clock gating were employed in GFDL shift digital control signals sequentially thus glitches were removed. Moreover, the proposed GFDL was used in the DLL supported 90°phase shifter to eliminate the glitches. The proposed DLL supported 90°phase shifter adopted SMIC 65 nm CMOS process with an active area of 0.018 mm² and the supply voltage of 1.2 V. HSPICE simulation results indicated that the proposed DLL supported 90° phase shifter had an operating frequency ranging from 217 MHz to 1GHz and consumed 2.8 mW at 1 GHz. The peak-to-peak and root-mean-square jitters of 90°phase-shifted clock were 17.77 ps and 5.16 ps respectively when a sine noise of 100 MHz and 30 mV was supplied. In addition, when the phase shifter track the process-voltage-temperature (PVT) variations, the outputted 90°phase-shifted clock effectively avoided glitch issues.