For the improvement of the spectral efficiency of traditional pulse position modulation (PPM) symbol, a novel Intra-Chip 4-PPM symbol is proposed, which not only achieves a communication rate of 1 Gbit/s, but also greatly reduces the required spectrum resources. While in demodulation, the bit error rate performance of this modulation symbol is greatly affected by the frequency offset between the transmitter’s clock and the receiver’s clock. To address this issue, an algorithm and a circuit are proposed to compensate for the symbol frequency offset, realize symbol synchronization and enable high-speed data demodulation in the analog domain. The circuit system compensates for the frequency offset by eliminating the initial phase difference between the received data and the local clock, extracting their frequency offset information, and periodically changing the instantaneous phase of the local clock. Meanwhile, the local clock is utilized to demodulate the received data in the third step. In order to improve the linearity of the phase interpolator (PI), a delay-locked loop with the PI is introduced in this paper. Within the interpolation range of 2π, the circuit achieves 32 interpolation intervals, a step size of 992, a resolution of 2.016 ps, the maximum differential nonlinearity (DNL) of 0.183°, and the maximum integral nonlinearity (INL) of 0.325°. In addition, the phase control algorithm proposed in this paper effectively avoids the output phase jump caused by current glitch. Based on UMC 40 nm CMOS RF LP process, simulation results show that the proposed algorithm and circuit reduce the frequency deviation between received data and local clock from 50×10^-6to 1.03×10^-6 and the accuracy of frequency offset compensation reach 97.94% in the typical corner, enabling a demodulation rate of 1 Gbit/s. This method has significant engineering application value for synchronization and demodulation of high-speed PPM data.