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Supervised by Ministry of Industry and Information Technology of The People''s Republic of China Sponsored by Harbin Institute of Technology Editor-in-chief Yu Zhou ISSNISSN 1005-9113 CNCN 23-1378/T

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Related citation:Fangxu Lü,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang.A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology[J].Journal of Harbin Institute Of Technology(New Series),2019,26(3):50-57.DOI:10.11916/j.issn.1005-9113.17104.
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A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology
Author NameAffiliation
Fangxu Lü Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Jianye Wang Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China 
Xuqiang Zheng The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Ziqiang Wang The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Yajun He The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Hao Ding Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China 
Yongcong Liu Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China 
Chun Zhang The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Zhihua Wang The Institute of Microelectronics, Tsinghua University, Beijing 100084, China 
Abstract:
A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented. The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST). The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control. In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation. The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing. The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI). In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption. Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm2. The measurement results show that this transceiver can achieve bit error rate (BER) < 10-12 after a 15.3 dB loss channel at 20 GHz.
Key words:  SerDes  transceiver  controller  PCS  PMA  CDR
DOI:10.11916/j.issn.1005-9113.17104
Clc Number:TN43
Fund:
Descriptions in Chinese:
  

40Gb/s高速串行接口收发芯片的设计

吕方旭1,2,王建业1,郑旭强1,王自强1

贺娅君1,丁浩1,刘勇聪1,张春1,王志华1

(1. 空军工程大学 防空反导学院,西安 710051;

2. 清华大学 微电子与纳电子学系,北京 100084)

摘要:

本文介绍了一种完整的40Gb/s高速串行收发芯片,该芯片包含控制器和物理层。控制器主要包含协议传输控制、前向纠错编码以及用户层的内建自测试电路。物理层中的媒体接入子层(PCS)主要支持64/66的编解码功能,物理层的内建自测试功能以及差分输出的P/N极性反转功能。物理层的媒体接入适配层(PMA)主要采用1/4速率架构来放宽收发机的时序约束。发射机采用一种新型的4:1MUX来降低发射机的功耗、抖动。接收机采用基于相位插值器的时钟数据恢复电路和二进制鉴相器实现对输入数据时钟的提取,并完成对数据的重定时和解复用。均衡电路采用基于多复用器的4抽头前馈均衡器和两级连续时间线性均衡器的组合。该芯片采用65nm CMOS工艺加工制造,芯片面积是12 mm2。测试结果标明,当该收发芯片工作在40Gb/s,且通过15.3dB信道衰减时,它的误码率小于10-12,此时整体功耗是890mW。

关键词:高速串行接口, 收发机, 控制器, 物理逻辑编码子层, 物理媒体接入适配层, 时钟数据恢复

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