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Supervised by Ministry of Industry and Information Technology of The People's Republic of China Sponsored by Harbin Institute of Technology Editor-in-chief Yu Zhou ISSNISSN 1005-9113 CNCN 23-1378/T

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Related citation:Shruti Kalra,Ruby Beniwal.Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design[J].Journal of Harbin Institute Of Technology(New Series),2022,29(4):70-80.DOI:10.11916/j.issn.1005-9113.2021141.
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Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design
Author NameAffiliation
Shruti Kalra Department of Electronics and Communication, Jaypee Institute of Information Technology, Noida 201307, India 
Ruby Beniwal Department of Electronics and Communication, Jaypee Institute of Information Technology, Noida 201307, India 
Abstract:
This paper presents a physics-based compact gate delay model that includes all short-channel phenomena prevalent at the ultra-deep submicron technology node of 32 nm. To simplify calculations, the proposed model is connected to a compact α-power law-based (Sakurai-Newton) model. The model has been tested on a wide range of supply voltages. The model accurately predicts nominal delays and the delays under process variations. It has been shown that at lower technology nodes, the delay is more sensitive to threshold voltage variations, specifically at the sub-threshold operating region as compared with effective channel length variations above the threshold region.
Key words:  statistical variation  analytical model  process variability  nanoscale CMOS  propagation delay
DOI：10.11916/j.issn.1005-9113.2021141
Clc Number:O29, O24, TN91
Fund:

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