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Supervised by Ministry of Industry and Information Technology of The People's Republic of China Sponsored by Harbin Institute of Technology Editor-in-chief Yu Zhou ISSNISSN 1005-9113 CNCN 23-1378/T

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Related citation:Shruti Kalra.Mathematical Insight into Moderate Inversion Gate Delay Variability for Ultradeep Submicron Digital Circuit Design[J].Journal of Harbin Institute Of Technology(New Series),2023,30(4):68-75.DOI:10.11916/j.issn.1055-9113.2022023.
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Mathematical Insight into Moderate Inversion Gate Delay Variability for Ultradeep Submicron Digital Circuit Design
Author NameAffiliation
Shruti Kalra Department of Electronics and Communication Engineering, Jaypee Institute ofInformation Technology, Noida 201307, India 
Abstract:
Voltage scaling has been extensively used in industry for decades to reduce power consumption. In recent years, exploring digital circuit operation in moderate inversion has created an interest among researchers due to its immense capability to provide a perfect tradeoff between high performance and low energy operation. But circuits operating in moderate inversion are susceptible to process variations and variability. To compute variability, statistical parameters such as the probability density function (PDF) and cumulative distribution function (CDF) are required. This paper presents an analytical model framework for delay calculations utilizing log skew normal distribution for ultradeep submicron technology nodes up to 22 nm. The CDF of the proposed model is utilized to calculate minimum and maximum delays with 3σ-accuracy providing better accuracy than the conventional methods. The obtained results are also compared with Monte Carlo simulations with errors lying within the acceptable range of 2%-4%.
Key words:  moderate inversion  ultradeep submicron  predictive technology model  variability  log skew normal distribution
DOI：10.11916/j.issn.1055-9113.2022023
Clc Number:TN91,TK01
Fund:

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