| Author Name | Affiliation | | Lidong Xing | School of Microelectronics, Xidian University, Xi’An 710071, China
School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’An 710121, China | | Tao Li | School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’An 710121, China | | Hucai Huang | School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’An 710121, China | | Jungang Han | School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’An 710121, China |
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| Abstract: |
| This paper studies some programming techniques for low power rendering for 3D graphics. These techniques are derived from analysis and simulation results of hardware circuits of GPU. Although low power 3D graphics hardware design has been studied by other researchers, low power programming techniques from hardware perspective have not been investigated in depth. There are many factors that affect 3D graphics rendering performance, such as the number of vertices, vertex sharing, level of details, texture mapping, and rendering algorithms. An analytical study of graphics rendering workload is performed and the effect of a number of programming tips such as vertex sharing, clock gating and buffering of unmoving or translational objects is deeply studied. The results presented in this paper can be used to guide 3D graphics programming for optimizing both power consumption and performance. |
| Key words: GPU 3D graphics rendering low power workload vertex sharing graphics programming |
| DOI：10.11916/j.issn.1005-9113.17036 |
| Clc Number:TP302 |
| Fund: |
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| Descriptions in Chinese: |
| 3D图形渲染功耗优化技术研究 邢立冬1,2，李 涛  ，黄虎才  ，韩俊刚 (1. 西安电子科技大学 微电子学院，西安 710071； 2．西安邮电大学 电子工程学院，西安 710121) 创新点说明：1） 对3D图形渲染管线的负载进行了分析，得到了影响渲染性能的顶点着色器和像素着色器负载之间的解析关系。 2） 从软件和硬件两个方面对3D图形渲染中的低功耗优化技术进行了研究，并给出了一些用于降低渲染能量的编程技术，主要包括顶点共享、时钟门控、LOD（Levels of Detail，多细节层次）技术和静态目标缓存等技术。 研究目的： 为对传统3D图形渲染结构进行研究，并对渲染管线的负载进行分析，提出适用于3D图形渲染的低功耗优化技术。 研究方法： 实验运行在我们自己设计的一款图形处理器芯片（Firefly 1）上，首先在Xilinx Virtex-7 XC7VX690T板上实现了FPGA原型，然后用SMIC 0.13μm CMOS工艺流片并测试成功。该芯片能够在200MHz运行，峰值性能为6.4Gflops，并通过OpenGL1.3测试。另外我们还构建了一个时钟精确的仿真和分析平台用于对图形处理器芯片的性能进行研究。为验证所提出的功耗优化技术的有效性，选取9个不同类型的渲染场景进行验证，通过使用Synopsys 的Power Compiler功耗分析工具、SMIC 0.13μm CMOS工艺库和VCS仿真器来执行仿真，分别得到不同测试程序执行时顶点着色器和像素着色器的实际功耗和能耗。 结果： 本文提出的低功耗优化技术可以显著的降低3D图形渲染的功耗和能耗，其中顶点着色器在所测试的9个程序上的功耗平均降幅可达64.6%，像素着色器功耗的平均降幅可达37.8%。 结论： 本研究成果可用于指导3D图形处理器的硬件设计和3D图形编程以优化系统功耗和性能。 关键词：GPU，3D图形渲染；低功耗；负载；顶点共享 |
