| 引用本文: | 韩津生,林家骏,叶建武,周文锦.FPGA的AES高速处理模型设计[J].哈尔滨工业大学学报,2012,44(3):128.DOI:10.11918/j.issn.0367-6234.2012.03.025 |
| HAN Jin-sheng,LIN Jia-jun,YE Jian-wu,ZHOU Wen-jin.Design of AES high-speed model on FPGA[J].Journal of Harbin Institute of Technology,2012,44(3):128.DOI:10.11918/j.issn.0367-6234.2012.03.025 |
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| FPGA的AES高速处理模型设计 |
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韩津生1, 林家骏1, 叶建武2, 周文锦3
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(1.华东理工大学 信息科学与工程学院, 200237 上海,daidaidou@163.com;2.东方通信股份有限公司,310053 杭州;3.天津市政府国际经济研究室,300041 天津);1.华东理工大学 信息科学与工程学院, 200237 上海,daidaidou@163.com;2.东方通信股份有限公司,310053 杭州;3.天津市政府国际经济研究室,300041 天津
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| 摘要: |
| 为了提高AES的处理速度,提出了AES的全流水线设计思想．通过对全流水线路径上相应MEM资源和逻辑资源的深入分析,找出制约数据块工作效率的因素,采用双通道运算模型,创建各流水线节点的高速模型,实现AES的全流水线设计．实验结果表明:在EP4CE40F29C8的FPGA芯片上执行AES加解密运算,其吞吐量达到7.2 Gbps．在全流水线架构下,双通道的设计思想使得流水线上的所有数据块处于高效工作状态,系统在低成本的前提下实现了性能的大幅提高． |
| 关键词: AES 全流水线 双通道 |
| DOI：10.11918/j.issn.0367-6234.2012.03.025 |
| 分类号:TG506.1 |
| 基金项目:国家自然科学基金资助项目（60903186）. |
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| Design of AES high-speed model on FPGA |
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HAN Jin-sheng,LIN Jia-jun,YE Jian-wu,ZHOU Wen-jin
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| Abstract: |
| To improve the performance of AES on FPGA, an idea of fully pipeline is proposed. After analyzing the needs of memory and logic elements deeply and finding out the factors restricting the efficiency of data blocks, the high-speed operation of the pipeline node model with dual channel mold is found to implement the AES full line. Experimental results show that the throughput of the AES encryption and decryption algorithm on FPGA of EP4CE40F29C8, can reach up to 7.2 Gbps. In the framework of fully pipeline, the idea of dual channel mold makes all the pipeline data blocks in efficient working condition. System under the premise of low-cost achieves a substantial improvement in performance. |
| Key words: AES fully pipeline dual channel |
