| 引用本文: | 徐力,吴新春,周彬,叶文霞.加速硬件木马检测方法研究[J].哈尔滨工业大学学报,2017,49(11):137.DOI:10.11918/j.issn.0367-6234.201611138 |
| XU Li,WU Xinchun,ZHOU Bin,YE Wenxia.Study on acceleration of hardware Trojan detection[J].Journal of Harbin Institute of Technology,2017,49(11):137.DOI:10.11918/j.issn.0367-6234.201611138 |
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| 摘要: |
| 为有效检测出芯片在设计和外包制造过程中是否被插入硬件木马电路, 提出一种在芯片设计阶段插入二选一数据选择器(MUX)来提高电路节点转移概率的方法.即在电路中转移概率低于转移概率阈值的候选节点的主要输入端插入MUX来提高相关节点的转移概率, 从而实现加速电路中硬件木马的检测.通过对扇出锥和电路逻辑拓扑结构的分析，选择对整个电路转移概率影响最大的节点作为候选节点，实现对MUX插入算法的优化，从而减少MUX的插入数量.同时增加关键路径延时限制，避免电路关键路径延迟超过预先设定的阈值.将预先设计的硬件木马电路的输入端插入在电路中转移概率较小的节点，并向电路输入端输入激励信号，分析计算在MUX插入前后电路转移概率变化以及硬件木马电路的激活概率. ISCAS'89基准电路的实验结果表明：在插入MUX之后，电路整体转移概率显著提高，电路中转移概率小于转移概率阈值的节点数明显降低；被插入在电路中的硬件木马被激活的概率显著提高；电路关键路径延时增加百分比控制在预先设定的比例因子之内.
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| 关键词: 二选一数据选择器 硬件木马 转移概率 路径延时 |
| DOI：10.11918/j.issn.0367-6234.201611138 |
| 分类号:TN407 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61100031) |
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| Study on acceleration of hardware Trojan detection |
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XU Li1,WU Xinchun1,ZHOU Bin2,YE Wenxia1
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(1.The School of Information Science and Technology, Southwest Jiao Tong University, Chengdu 611756, China; 2.Research Center of Basic Space Science, Harbin Institute of Technology, Harbin 150001, China)
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| Abstract: |
| In order to effectively detect whether the chip is inserted into the hardware Trojan circuit during the design and manufacturing process, a method is proposed to increase the transition probability of the circuit nodes by inserting 2-to-1 MUXs in the chip design stage. The main input of the candidate node whose transition probability is lower than the transition probability threshold is inserted into the MUX to improve the transition probability of the relevant nodes, so as to realize acceleration of hardware Trojan detection in the circuit. The optimization of the insertion algorithm is realized by analyzing the fan-out cone and logic topology, and the node with the greatest influence on the transition probability of the whole circuit is selected as the candidate node, thus the number of MUXs insertion is reduced. Meanwhile, the critical path delay limit is increased to avoid the critical path delay of the circuit exceeding the preset threshold. The input terminals of the pre-designed hardware Trojan circuit are inserted into the nodes with small transition probability in the circuit, and the excitation signal is inputted to the input terminals of the circuit to analyze the change of the circuit's transition probability and the activation probability of the hardware Trojan circuit before and after the MUX insertion. The experimental results of the ISCAS'89 reference circuit show that the number of nodes whose transition probability is less than the transition probability threshold in the circuit is significantly lower; the probability of the inserted hardware Trojan being activated is significantly improved; the increased percentage of circuit critical path delay is controlled within a preset scale factor.
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| Key words: 2-to-1 MUX hardware Trojan transition probability path delay |
