| 引用本文: | 姚亚峰,邹凌志,王巍,钟梁.低消耗免查找表CORDIC算法[J].哈尔滨工业大学学报,2017,49(11):109.DOI:10.11918/j.issn.0367-6234.201704019 |
| YAO Yafeng,ZOU Lingzhi,WANG Wei,ZHONG Liang.Low-consumption andLUT-omitted CORDIC algorithm[J].Journal of Harbin Institute of Technology,2017,49(11):109.DOI:10.11918/j.issn.0367-6234.201704019 |
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| 摘要: |
| 为减少传统流水线型CORDIC(Coordinate Rotation Digital Computer)算法的硬件资源消耗和输出时延，在包含查找表的三阶段CORDIC算法实现基础上，提出一种免去查找表环节的CORDIC算法实现方法.提出的改进算法直接使用四次移位相加的迭代运算替换查找表结构从而显著降低寄存器消耗，同时通过合并迭代降低迭代次数进而有效减少最大输出时延，并综合运用角度二极化重编码(Binary To Bipolar Recoding, BBR)方法和角度区间折叠技术保证了输出精度.使用Verilog HDL语言在ISE14.2软件平台上对三种算法进行具体实现，利用XST工具对其进行综合，并通过MATLAB建模计算得到算法的正余弦值输出误差.仿真实验结果表明：在输出位宽均设置为16位的情况下，免查找表CORDIC算法能够有效地输出正余弦值；与传统流水线型算法相比，免查找表算法的寄存器资源消耗减少大约74.42%，计算所需的时钟周期降低68.75%，其输出精度也有明显改善；与三阶段算法相比，免查找表算法的寄存器消耗减少大约43.3%.本文提出的免查找表CORDIC算法具有实时性强、输出精度高、硬件资源消耗少等优势，更适用于高速实时的现代数字通信系统应用.
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| 关键词: 坐标旋转数字计算机 免查找表 二极化重编码 可编程逻辑门阵列 数字信号处理 |
| DOI：10.11918/j.issn.0367-6234.201704019 |
| 分类号:TN492 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61601334) |
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| Low-consumption andLUT-omitted CORDIC algorithm |
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YAO Yafeng,ZOU Lingzhi,WANG Wei,ZHONG Liang
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(Faculty of Mechanicaland Electronic Information, China University of Geosciences, Wuhan 430074, China)
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| Abstract: |
| In order to reduce the hardware resource consumption and output delay in the conventional pipeline CORDIC (Coordinate Rotation Digital Computer) algorithm, a LUT-omitted CORDIC algorithm is proposed on the basis of the three-stage CORDIC with look-up table (LUT). The proposed new algorithm adopts 4 iterations of shifter-adder instead of LUT to reduce the register consumption apparently, and merges some iterations to decrease the output delay effectively, and guarantees the output resolution by using a combination of Binary to Bipolar Recoding (BBR) and angle range folding. The improved algorithm is specifically implemented using Verilog HDL on ISE 14.2 software platform and synthesized using XST tools, and is modeled to analyze the output errors through MATLAB. Simulation experiment results show that the register resource consumption of the new algorithm, producing sine/cosine effectively, is reduced by about 74.42% compared with the conventional one, while the output width is set to 16 equally. The computing clock periods are decreased by 68.75%, and the resolution is also improved obviously. Compared with the three-stage algorithm, the consumption of register is reduced by about 43.3%. The proposed algorithm has some advantages such as brilliant real-time performance, high resolution, and low consumption. And it is more applicable for modern digital communication systems that demand for high speed and promising real-time performance.
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| Key words: coordinate rotation digital computer to omit look-up table binary to bipolar recoding field-programmable gate array digital signal processing |
