| 引用本文: | 侯强,揭灿,姚亚峰,钟梁.一种结合高分辨率TDC的快速全数字锁相环设计[J].哈尔滨工业大学学报,2018,50(11):83.DOI:10.11918/j.issn.0367-6234.201803148 |
| HOU Qiang,JIE Can,YAO Yafeng,ZHONG Liang.A fast all digital phase-locked loop design with high resolution TDC[J].Journal of Harbin Institute of Technology,2018,50(11):83.DOI:10.11918/j.issn.0367-6234.201803148 |
|
| 摘要: |
| 针对时间数字转换器(Time-to-Digital Converter，TDC)的分辨率较低，全数字锁相环(All Digital Phase-Locked Loop，ADPLL)锁定参考信号的时间较长等问题，提出一种在高精度TDC基础上快速实现锁定的全数字锁相环.提出的时间数字转换器运用抽头延迟线法和双通道差分延迟线法提高量化精度，采用对称式层次型结构实现对负时间间隔的量化，设计的相调电路将量化的脉冲信号还原为时间长度信号，通过状态机对反馈信号的相位提前或延迟，实现对参考信号的快速锁定，在环路锁定后使用下降沿检测电路适时关闭鉴频鉴相器和时间数字转换器，降低整体电路的功耗.在Xilinx KC705开发平台上进行仿真与验证，并在Xpower软件上与传统的基于游标尺链型的全数字锁相环进行功耗对比分析.结果表明，此全数字锁相环的量化误差控制在0.2 ns之内，反馈信号可在3个参考信号时钟周期内快速锁定参考信号，整体电路功耗相比传统的基于游标尺链型的全数字锁相环降低约18.1%.本文提出的全数字锁相环具有实时性强、锁定速度快、量化精度高、功耗低等优势，更适用于高速、低功耗的现代数字通信系统.
|
| 关键词: 全数字锁相环 时间数字转换器 数控振荡器 抽头延迟线法 双通道差分延迟线法 |
| DOI：10.11918/j.issn.0367-6234.201803148 |
| 分类号:TN492 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61601334)； 中央高校军民融合专项基金培育项目(201708) |
|
| A fast all digital phase-locked loop design with high resolution TDC |
|
HOU Qiang,JIE Can,YAO Yafeng,ZHONG Liang
|
|
（School of Mechanical and Electronic Information, China University of Geosciences, Wuhan 430074, China）
|
| Abstract: |
| Aiming at the problems that time-to-digital converter(TDC)suffers a low resolution and all digital phase-locked loop(ADPLL)takes a longer time to lock reference signal, this paper proposes a fast locking ADPLL based on high precision TDC. The new TDC employs tapped delay line method and double-channel differential delay line method to improve quantization accuracy, and uses symmetric hierarchical structure to quantize negative time interval. Meanwhile, the proposed phase modulation circuit recovers quantitative pulse signal into time span signal, and advances or delays phase of feedback signal by state machine to achieve fast locking on reference signal. Moreover, it applys detection circuit of falling edge to turn off phase frequency detector and TDC, which reduce the power consumption of the entire circuit at proper time. Simulation and verification are carried out in the Xilinx KC705 development kit, and contrastive analysis on power consumption is provided between new design and traditional ADPLL based on vernier chain in Xpower software. The results show that quantization error of new ADPLL is restricted within 0.2 ns. Besides, feedback signal can rapidly lock the reference signal in three reference signal clock periods. Power consumption of the overall circuit is cut down by approximately 18.1% compared to traditional ADPLL based on vernier chain. The proposed ADPLL has the advantages of strong real-time performance, high locking speed, high quantitative precision and low power consumption, and it is more applicable for modern digital communication systems that demand for high speed and low power consumption.
|
| Key words: all digital phase-locked loop time-to-digital converter digital controlled oscillator tapped delay line method double-channel differential delay line method |
