| 引用本文: | 王国洪,宛强,姚亚峰,钟梁.精确频率输出的超低时延DDS电路设计[J].哈尔滨工业大学学报,2019,51(5):44.DOI:10.11918/j.issn.0367-6234.201805108 |
| WANG Guohong,WAN Qiang,YAO Yafeng,ZHONG Liang.A DDS circuit design with ultra-low latency and exact output frequency[J].Journal of Harbin Institute of Technology,2019,51(5):44.DOI:10.11918/j.issn.0367-6234.201805108 |
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| 摘要: |
| 使用CMOS工艺设计高性能、低成本的直接数字频率合成器DDS是一项十分具有挑战性的任务.本文提出了一种模数可编程的超低时延DDS电路设计.通过增加一个辅助相位累加器,可以根据输出频率的需要来设置辅助相位累加器的输入和模数配置来产生小数复合频率控制字,从而可以进行各种频率的精确输出,完全消除了输出频率误差.还针对CORDIC算法进行了优化改进,提出了一种仅需要小容量的查找表和简单角度校正的CORDIC实现方法,免除了迭代运算过程,设计了一种超低时延的相位幅度转换电路.在电路资源消耗没有增加的前提下,设计电路不仅实现了精确频率输出,还大大降低了电路的输出时延.验证结果表明:本DDS设计电路输出频率不存在频率误差,并且只需要两个时钟周期就能得到高精度的正余弦波输出.本设计通过对相位累加器和相位幅度转换电路的改进,消除了输出频率误差和降低了输出时延,具有输出频率精确、输出时延小、成本低等优点,更加适合输出频率精度要求高、实时性强的信号处理应用场合. |
| 关键词: 模数可编程 相位幅度变换 坐标旋转数字计算 直接数字频率合成 数字电路设计 |
| DOI：10.11918/j.issn.0367-6234.201805108 |
| 分类号:TN492 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61601334)；中央高校军民融合专项基金培育项目(201708) |
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| A DDS circuit design with ultra-low latency and exact output frequency |
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WANG Guohong,WAN Qiang,YAO Yafeng,ZHONG Liang
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(School of Mechanical and Electronic Information China University of Geosciences, Wuhan 430074, China）
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| Abstract: |
| The design of a high-performance and low-cost direct digital frequency synthesizer (DDS) by using complementary metal oxide semiconductor (CMOS) technology is a challenging task. This paper presents a programmable modular and ultra-low latency DDS circuit design. By adding an auxiliary phase-accumulator, the input of the auxiliary accumulator and the analog-digital configuration can be set to generate the fractional composite frequency control word based on the need of the output frequency, so that accurate output of various frequencies can be performed and the output frequency error is completely eliminated. The coordinate rotation digital computer (CORDIC) algorithm was optimized and improved to propose a CORDIC implementation which only needs a small capacity lookup table and simple angle correction. It eliminates the iterative operation process and designs an ultra-low delay phase-amplitude conversion circuit. Under the premise that the circuit resource consumption is not increased, the design circuit not only realized the accurate frequency output, but also greatly reduced the output delay of the circuit. The verification results show that the output frequency of the DDS design circuit did not have a frequency error, and it took only two clock cycles to obtain a high-precision sine cosine wave output. This design improves the phase-accumulator and phase-amplitude conversion circuit, eliminates output frequency error, reduces output delay, and has the advantages such as accurate output frequency, small output delay, and low cost. Therefore, it is more suitable for signal processing applications with high output frequency accuracy and real-time performance. |
| Key words: programmable modular phase-amplitude conversion coordinate rotation digital computer direct digital frequency synthesis digital circuit design |
