| 引用本文: | 康婧,安军社,王冰冰,张伟东.卫星VCM数传高效低功耗LDPC编码器[J].哈尔滨工业大学学报,2021,53(2):14.DOI:10.11918/202003011 |
| KANG Jing,AN Junshe,WANG Bingbing,ZHANG Weidong.High efficient and low power LDPC encoder for VCM-based satellite data transmissions[J].Journal of Harbin Institute of Technology,2021,53(2):14.DOI:10.11918/202003011 |
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| 卫星VCM数传高效低功耗LDPC编码器 |
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康婧1,2,安军社1,王冰冰1,2,张伟东1,2
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(1.中国科学院复杂航天系统电子信息技术重点实验室(中国科学院国家空间科学中心), 北京 100190; 2.中国科学院大学, 北京 100190)
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| 摘要: |
| 随着空间探测任务需求愈加复杂,卫星有效载荷传感器精度不断提高,星地链路传输数据量大幅增加.为满足近地轨道(low Earth orbit, LEO)卫星可变编码调制(variable coding modulation, VCM)数传系统对高通量、低功耗、高可靠性信道编码应用需求,提出了一种基于第二代数字视频广播(the second generation digital video broadcast, DVB-S2)标准的快速累加并向递归编码算法,同时基于此算法提出了一种高效低功耗低密度奇偶校验码(low-density parity-check, LDPC)编码器.利用输入信息比特随机性以及二进制计算特点简化校验比特中间变量的计算,降低了编码器的功耗；通过分析不同VCM模式中LDPC码的相似性,重复利用校验比特中间变量计算单元和存储器,提高了硬件资源利用率；通过控制模块动态重构编码器兼容3种VCM模式,并在保证编码正确性前提下进行模式切换,提高了编码器的灵活性；采用与调制方式相匹配的校验比特存储方案按顺序输出M个并行比特,提高了编码数据吞吐率,具有高效性.在Xilinx XC7K325t-3fbg900 FPGA上对提出的编码器进行了实现,结果表明:在347.5 MHz系统工作时钟下,编码数据吞吐率最高可达1.104 Gb/s,数据吞吐量较固定编码调制系统(constant coding modulation, CCM)提高了31.9%,且该编码器功耗与相同平台同类编码器相比降低了21.7%. |
| 关键词: LDPC编码器 VCM DVB-S2标准 低功耗 FPGA |
| DOI：10.11918/202003011 |
| 分类号:TN911.22 |
| 文献标识码:A |
| 基金项目:中国科学院空间科学先导卫星专项(XDA15320100) |
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| High efficient and low power LDPC encoder for VCM-based satellite data transmissions |
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KANG Jing1,2,AN Junshe1,WANG Bingbing1,2,ZHANG Weidong1,2
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(1.Key Laboratory of Electronics and Information Technology for Space Systems (National Space Science Center, Chinese Academy of Sciences), Beijing 100190, China;2.University of Chinese Academy of Sciences, Beijing 100190, China)
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| Abstract: |
| With the increasing complexity of space exploration requirements and the development of high-resolution payloads, satellite-ground downlink data transmission systems have been requested for transmitting increasing volumes of data. In order to meet the requirements of high throughput, low power, and high reliability for variable coding modulation (VCM) transmission systems of low Earth orbit (LEO) satellites, a new fast accumulated parallel recursive low-density parity-check (LDPC) encoding algorithm based on the second generation digital video broadcast (DVB-S2) standard was proposed, and an efficient encoder with low power was designed. The encoder was lower power consumed by simplifying the intermediate variables of parity-check bits based on the randomness of input information bits and the characteristic of binary operation. By analyzing the similarities between different LDPC codes and reusing the computation units and memories, the utilization of hardware resources was improved. Benefitting from the dynamic encoder structure, the encoder was compatible with three VCM modes, and the correctness was guaranteed when VCM modes changed, which increased the flexibility of the encoder. Furthermore, the new parity-check bits storage schemes that match with the modulation mode could output M parallel bits in sequence and increase the encoder throughput with high efficiency. The proposed encoder design was implemented on the Xilinx XC7K325t-3fbg900 FPGA, and experimental results showed that the maximum encoding throughput was up to 1.104 Gb/s when operating at a system clock of 347.5 MHz, the total throughput was improved by 31.9% compared with the constant coding modulation (CCM) transmission system, and the power consumption of the encoder was reduced by 21.7%. |
| Key words: LDPC encoder VCM DVB-S2 standard low power FPGA |
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