| 引用本文: | 史柱,肖筱,王斌,杨博,卢红利,岳红菊,刘文平.一种先进CMOS工艺下抗单粒子瞬态加固的与非门[J].哈尔滨工业大学学报,2023,55(5):114.DOI:10.11918/202109131 |
| SHI Zhu,XIAO Xiao,WANG Bin,YANG Bo,LU Hongli,YUE Hongju,LIU Wenping.A radiation hardened NAND gate against single-event transient in advanced CMOS process[J].Journal of Harbin Institute of Technology,2023,55(5):114.DOI:10.11918/202109131 |
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| 一种先进CMOS工艺下抗单粒子瞬态加固的与非门 |
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史柱1,肖筱1,2,王斌1,2,杨博1,2,卢红利1,2,岳红菊1,2,刘文平1,2
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(1.西安微电子技术研究所,西安 710065;2.抗辐射集成电路国防科技重点实验室(西安微电子技术研究所),西安 710065)
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| 摘要: |
| 先进纳米集成电路工艺的发展使得微电子器件翻转的阈值电荷不断降低,导致数字电路中由单粒子效应引起的软错误率增加。为加强集成电路中标准单元的抗辐射特性,本文提出了一种抗单粒子瞬态(single-event transient,SET)加固的与非门结构。在三阱工艺下,通过将下拉网络中每一个NMOS管的衬底和源极各自短接,便有效地提高了与非门抗辐射性能,而且随着输入端数目的增加,本文提出的与非门加固效果更加明显。利用Sentaurus TCAD软件的混合仿真模式进行粒子入射仿真实验,对于与输出节点相连的NMOS管采用经过工艺校准的三维物理模型,其他MOS管采用工艺厂商提供的Spice模型。结果显示:在40 nm工艺下,当入射粒子 线性能量传输(linear energy transfer,LET)值为10 MeV·cm2/mg时,本文提出的2输入与非门能够在3种输入的情况下降低输出电压扰动幅度。其中在N2管关闭的输入模式下,达到了对单粒子入射免疫的效果；对于3输入与非门,即使在“最坏”输入的情况下,也能使输出电压翻转幅度降低85.4%。因此,本文提出的与非门加固方法起到了显著的抗单粒子瞬态效果。 |
| 关键词: 辐射加固 单粒子瞬态 组合逻辑 与非门 工艺 |
| DOI：10.11918/202109131 |
| 分类号:TN43 |
| 文献标识码:A |
| 基金项目:国家重大专项资助(414240102033) |
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| A radiation hardened NAND gate against single-event transient in advanced CMOS process |
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SHI Zhu1,XIAO Xiao1,2,WANG Bin1,2,YANG Bo1,2,LU Hongli1,2,YUE Hongju1,2,LIU Wenping1,2
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(1.Xi’an Microelectronics Technology Institute, Xi’an 710065, China; 2.National Key Laboratory of Science and Technology on Radiation-Hardened Integrated Circuits (Xi’an Microelectronics Technology Institute), Xi’an 710065, China)
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| Abstract: |
| The development of advanced nano-integrated circuit processes has led to a decreasing threshold charge in microelectronic devices, resulting in an increased rate of soft errors caused by single-event effects in digital circuits. To enhance the radiation resistance of standard cells in integrated circuits, this paper proposes a NAND gate structure that is resistant to single-event transients (SETs). In the triple well process, by shorting the substrate and source of each NMOS transistor in the pull-down network, the radiation resistance of the NAND gate was effectively improved, and the hardening of the proposed NAND gate became more effective as the number of inputs increased. Particle incidence simulation experiments were performed by Sentaurus TCAD software in hybrid simulation mode. For the NMOS transistor connected to the output node, the three-dimensional physical model that has been calibrated by the process was used, and the Spice model provided by the manufacturer was adopted for other MOS transistors. Simulation results show that the proposed two-input NAND in 40 nm process could reduce the output voltage fluctuation amplitude in three-input cases at the linear energy transfer (LET) value of incidence particle of 10 MeV·cm2/mg. Besides, the effect of immunity to single particle incidence was achieved in the input mode with N2 transistor closed. For the hardened three-input NAND gate, the output voltage disturbance could be reduced by up to 85.4% even in the “worst case”. Therefore, the proposed hardening method for NAND gate has a significant effect against SET. |
| Key words: radiation hardening single-event transient (SET) combinational logic circuit NAND gate process |
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