| 引用本文: | 徐超,吴灯鹏,李新昌,徐大伟,俞跃辉,程新红.带有修调的分段曲率补偿带隙基准电路[J].哈尔滨工业大学学报,2020,52(4):112.DOI:10.11918/201902037 |
| XU Chao,WU Dengpeng,LI Xinchang,XU Dawei,YU Yuehui,CHENG Xinhong.Piecewise curvature compensated bandgap reference circuit with trimming procedure[J].Journal of Harbin Institute of Technology,2020,52(4):112.DOI:10.11918/201902037 |
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| 带有修调的分段曲率补偿带隙基准电路 |
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徐超1,2,3,吴灯鹏1,3,李新昌1,3,徐大伟1,3,俞跃辉1,3,程新红1,3
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(1.中国科学院上海微系统与信息技术研究所,上海 200050; 2.上海科技大学 物理科学与技术学院,上海 201210; 3.中国科学院大学,北京 100049)
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| 摘要: |
| 为得到高精度低温度系数、高电源抑制比的基准电压,同时为了降低工艺中非理想性因素的影响,设计了一种新的带有修调的分段曲率补偿基准电路. 通过利用电阻分压和工作在亚阈值区域的MOSFET的电学特性,产生正温度系数和负温度系数的电流,在高温段和低温段分别对带隙基准电压进行曲率补偿,提出了一种新的快速优化基准电压温度系数的芯片级修调方法,包含温度系数修调和电压幅值修调,可以快速获得最低温度系数对应码值以提升工作效率.基于0.35 μm BCD工艺,流片验证了该修调方案的可行性.结果表明:在-40℃~125℃内,基准电压最低仿真温度系数为0.84×10-6/℃,最低实测温度系数为5.33×10-6/℃,随机抽样结果显示温度系数的平均值为7.47×10-6/℃;采用基于计算斜率的修调方法,测试10块芯片的平均修调次数为3.5次,与使用逐次逼近的修调方法相比,效率提升59.8％;低温度系数的带隙基准电压有利于提升电池管理芯片对电池剩余电量估算的准确性,该带隙基准电路已成功应用于电池管理芯片内高精度模数转换器中. |
| 关键词: 分段曲率补偿 修调 基准 温度系数 芯片级修调 |
| DOI：10.11918/201902037 |
| 分类号:TN433 |
| 文献标识码:A |
| 基金项目:国家重点研发计划(2016YFB0100700) |
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| Piecewise curvature compensated bandgap reference circuit with trimming procedure |
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XU Chao1,2,3,WU Dengpeng1,3,LI Xinchang1,3,XU Dawei1,3,YU Yuehui1,3,CHENG Xinhong1,3
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(1.Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China; 2.School of Physical Science and Technology, ShanghaiTech University, Shanghai 201210, China; 3.University of Chinese Academy of Sciences, Beijing 100049, China)
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| Abstract: |
| To obtain bandgap reference voltage with high PSRR, high precision, and low temperature coefficient and meanwhile reduce the influence of non-ideal factors in the process, a piecewise curvature compensated bandgap reference circuit with a trimming procedure was proposed. The current with positive and negative temperature coefficients was generated by utilizing the resistor divider and the electrical characteristics of the MOSFET operating in the subthreshold region. The bandgap reference voltage was compensated at high temperature and low temperature respectively. A new chip-level trimming method including temperature coefficient trimming and voltage amplitude trimming for rapidly optimizing the reference voltage temperature coefficient, which can quickly acquire the code value of the lowest temperature coefficient curve and improve work efficiency. Based on 0.35 μm Bipolar-CMOS-DMOS (BCD) process, the chip was taped out to verify the feasibility of the trimming scheme. Simulation and test results show that: from -40℃ to 125℃, the lowest simulated reference voltage temperature coefficiency was 0.84×10-6/℃, the lowest measured temperature coefficiency was 5.33×10-6/℃, and the average temperature coefficiency was 7.47×10-6/℃ according to ramdom sampling. The average trimming times for ten chips was 3.5 by using the method based on calculating the slope. The efficiency was improved by 59.8％ compared with the method of successive approximation. The bandgap reference voltage with low temperature coefficient is helpful to improve the accuracy of the battery management chip in estimating battery residual power. This circuit has been successfully applied to high precision analog-to-digital converter in battery management chips. |
| Key words: piecewise curvature compensated trimming reference temperature coefficient chip-level trimming |
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