| 引用本文: | 乔冰涛,吴旭凡,刘海静,王正,董业民.双模冗余汉明码的设计与验证[J].哈尔滨工业大学学报,2020,52(10):161.DOI:10.11918/202001018 |
| QIAO Bingtao,WU Xufan,LIU Haijing,WANG Zheng,DONG Yemin.Design and verification of dual modular redundancy hamming code[J].Journal of Harbin Institute of Technology,2020,52(10):161.DOI:10.11918/202001018 |
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| 双模冗余汉明码的设计与验证 |
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乔冰涛1,2,吴旭凡1,刘海静1,王正1,董业民1,2
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(1.信息功能材料国家重点实验室(中国科学院 上海微系统与信息技术研究所),上海,200050; 2.材料与光电研究中心(中国科学院大学),北京 100049)
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| 摘要: |
| 集成电路芯片工作在电磁环境复杂的空间环境中,容易受到高能粒子的影响发生软错误.在芯片内,存储单元所占面积超过一半以上,对存储器单元进行加固是提升芯片可靠性的重要途径之一.因此,本文对汉明码做出改进,提出了一种双模冗余汉明码,该方法能够修正存储单元中出现的一位翻转和两位翻转.首先,对汉明码编码模块进行逻辑优化,有效减少了编码电路的延迟,再把该模块生成的校验码进行双模冗余处理,作为双模冗余汉明码编码模块的输出.之后依据汉明码解码规则分别对每份校验码与原码的组合进行处理,得到修正后的数据位与两位翻转标志位.通过分析发现当两位翻转未同时发生在原码内时,可以依据两位错误标志位的值得到正确的输出.最后,采用版图分割技术消除了两位原码同时翻转的情况,进一步提高了存储器的可靠性.在本文中,分别实现了字长为4、8和11的双模冗余汉明码,并与其它修正码的性能进行比较,结果表明:它们的电路延迟分别为8位字长汉明码的85%、89%和96%,低于两位修正能力的BCH码. |
| 关键词: 双模冗余 纠错码 高可靠 存储器 两位翻转 |
| DOI：10.11918/202001018 |
| 分类号:TP302.8 |
| 文献标识码:A |
| 基金项目:中科院重点部署项目(KGFZD-135-16-015) |
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| Design and verification of dual modular redundancy hamming code |
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QIAO Bingtao1,2,WU Xufan1,LIU Haijing1,WANG Zheng1,DONG Yemin1,2
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(1.State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences), Shanghai 200050, China; 2. Center of Materials Science and Optoelectronics Engineering (University of Chinese Academy of Sciences), Beijing 100049, China)
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| Abstract: |
| Integrated circuit chips work in complicated electromagnetic environments, which is susceptible to soft errors caused by high-energy particles. In a chip, the memory accounts for more than half of the total area, making it important to improve the reliability of the processor by hardening the memory. Therefore, a dual modular redundancy hamming (DMRH) code is designed and proposed in this paper, which can mitigate one-bit and two-bit upset in memory. First, logic optimization was carried out in the hamming code encoder to reduce the delay of the circuit, and the parity generated by this module was processed with dual modular redundancy technology, which was used as the output of the DMRH encoder. Then, the combinations of each parity and original code were processed according to the hamming decoding rules, and the revised data and two-bit upset flag were obtained. Through analysis, it was found that when the two-bit upset did not happen in the original code at the same time, the correct output could be obtained according to the two-bit upset flag. Finally, the layout segmentation technology was used to suppress the two-bit upset in the original code, which further improved the reliability of the memory. In this study, three types of DMRH codes with word lengths of 4,8, and 11 were realized. Compared with other correction codes, results show that the circuit delay of the codes obtained in this study was 85%, 89%, and 96% of the eight-bit hamming code, which was lower than the BCH codes. |
| Key words: dual modular redundancy error correction code high reliability memory two-bit upset |
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