| 引用本文: | 陈嘉豪,李浩明,王腾佳,王志宇,刘家瑞,郁发新.一种集成占空比校准的低杂散参考时钟倍频器[J].哈尔滨工业大学学报,2021,53(6):86.DOI:10.11918/201909034 |
| CHEN Jiahao,LI Haoming,WANG Tengjia,WANG Zhiyu,LIU Jiarui,YU Faxin.A low-spur reference frequency doubler with hybrid duty cycle calibration[J].Journal of Harbin Institute of Technology,2021,53(6):86.DOI:10.11918/201909034 |
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| 摘要: |
| 为降低小数分频模拟锁相环的相位噪声,并改善采用传统异或门倍频器对参考时钟进行倍频时引起的锁相环输出杂散,提出了一种集成占空比校准的低杂散参考时钟倍频器. 该倍频器对输入时钟进行倍频后输出参考时钟到锁相环,通过降低锁相环的分频比有效降低了锁相环输出信号的相位噪声. 针对由倍频器输入时钟占空比误差引起的参考时钟频率抖动及锁相环输出杂散恶化,该倍频器通过数控边沿调整技术在较大误差范围内进行占空比粗调,然后通过模拟占空比校准环路进行高精度占空比校准,两种校准方式根据所提出的占空比校准控制算法协同工作,在扩大校准范围的同时提高了校准精度. 仿真结果证明可以将100 MHz输入参考时钟占空比误差从13.8%降低至0.007%,且倍频输出频率误差低至380×10-6.基于40 nm CMOS工艺对该倍频器进行流片验证,测试结果表明:该倍频器能够使锁相环输出信号的带内噪声降低约6.67 dB,量化噪声降低约5.61 dB,且占空比校准后,能够将锁相环输出信号频谱中距离载波1/2参考时钟频率偏移处的杂散降低约9.52 dB;通过倍频器对锁相环的参考时钟进行倍频能够有效降低锁相环的带内噪声和量化噪声,对倍频器输入时钟的占空比进行校准能够有效降低锁相环输出频谱中的杂散. |
| 关键词: 占空比校准环路 倍频器 参考时钟 锁相环 杂散 |
| DOI：10.11918/201909034 |
| 分类号:TN432 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61604128) |
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| A low-spur reference frequency doubler with hybrid duty cycle calibration |
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CHEN Jiahao,LI Haoming,WANG Tengjia,WANG Zhiyu,LIU Jiarui,YU Faxin
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(Institute of Astronautic Electronic Engineering, Zhejiang University, Hangzhou 310027, China)
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| Abstract: |
| To reduce the phase noise of fractional-N phase locked loops (PLLs) and suppress the output spurs of PLLs caused by doubling the frequency of reference clock with traditional exclusive-OR gates (XOR), a low-spur reference frequency doubler (RFD) with a hybrid duty cycle calibration loop (DCCL) was proposed. The RFD doubles the frequency of input clock and outputs the reference clock to the PLL, effectively suppressing the phase noise of the PLL by reducing the divide ratio. To reduce the frequency jitter of the reference clock and the output spurs of the PLL caused by the duty cycle deviation of the input clock, the RFD first roughly calibrates the duty cycle with a digital-controlled edge adjustor and then improves the precision with an analog DCCL. The two methods work collaboratively based on the proposed controlling algorithm, achieving a wider calibration range and a higher precision simultaneously. Simulation results show that the proposed RFD could reduce the duty cycle error of a 100 MHz input clock from 13.8% to 0.007%, and decrease the output frequency error to 380×10-6. The circuit was fabricated in a 40 nm CMOS process. Test results show that it could suppress the in-band phase noise by 6.67 dB and quantization noise by 5.61 dB, and after the duty cycle calibration, the spurs at 1/2 reference frequency offset in the output signal spectrum of the PLL were reduced by 9.52 dB. The in-band noise and quantization noise of PLLs could be reduced by doubling the frequency of the reference clock of PLLs. The spurs in the output signal spectrum of PLLs could be suppressed efficiently by calibrating the input duty cycle of the RFD. |
| Key words: duty cycle calibration loop (DCCL) frequency doubler reference clock phase locked loops spur |
