| 引用本文: | 梁承托,梁利平,王志君.一种无毛刺DLL型90°移相器设计[J].哈尔滨工业大学学报,2019,51(10):68.DOI:10.11918/j.issn.0367-6234.201808088 |
| LIANG Chengtuo,LIANG Liping,WANG Zhijun.Design of a glitch free DLL supported 90°phase shifter[J].Journal of Harbin Institute of Technology,2019,51(10):68.DOI:10.11918/j.issn.0367-6234.201808088 |
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| 摘要: |
| 延时锁相环（delay look loop,DLL）型90°移相器广泛应用于双倍数据率同步动态存储器（double data rate synchronous dynamic random access memory,DDR SDRAM）中对时钟信号进行90°相移,实现数据双沿采样,以提高数据传输速率.数控延时线是DLL型90°移相器的重要组成部分.为解决传统数控延时线在延时调节过程中产生毛刺的问题,分析了传统数控延时线产生毛刺的原因,并提出一种结合锁存器和时钟门控单元的无毛刺数控延时线.引入锁存器和时钟门控使该无毛刺数控延时线的数字控制信号有序进行状态切换,达到抑制毛刺产生的目的.另外,将提出的无毛刺数控延时线应用于DLL型90°移相器中,成功消除了90°相移时钟的毛刺.设计采用SMIC 65 nm工艺来实现,供电电压为1.2 V,版图面积为0.018 mm2,用HSPICE进行仿真,结果表明:该移相器的工作频率范围为217 MHz~1 GHz,工作在1 GHz时,功耗为2.8 mW；供电电压添加100 MHz 30 mV正弦波噪声时,90°相移时钟的抖动峰峰值和均方根值分别为17.77 ps和5.16 ps.而且,移相器在进行工艺、电压、温度（process-voltage-temperature,PVT）跟随调节过程中,输出的90°相移时钟可有效避免毛刺问题. |
| 关键词: 无毛刺 数控延时线 双倍数据率 延时锁相环 移相器 |
| DOI：10.11918/j.issn.0367-6234.201808088 |
| 分类号:TN495 |
| 文献标识码:A |
| 基金项目:国家自然科学基金(61471354) |
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| Design of a glitch free DLL supported 90°phase shifter |
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LIANG Chengtuo1,2,LIANG Liping1,WANG Zhijun1
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(1.Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China; 2.University of Chinese Academy of Sciences, Beijing 100049, China)
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| Abstract: |
| Delay lock loop (DLL) supported 90°phase shifters are widely used in double data rate synchronous dynamic random access memory (DDR SDRAM) to generate 90°phase-shifted clock, which achieves double data rate sampling and improves data-rate. Digitally controlled delay line (DCDL) plays a critical role in the DLL supported 90°phase shifter. To remove glitches in traditional DCDL during the process of delay adjustment, the causes of glitches generation were analyzed, and a glitch free digitally controlled delay line (GFDL) with latch and clock gating was proposed. The latch and clock gating were employed in GFDL shift digital control signals sequentially thus glitches were removed. Moreover, the proposed GFDL was used in the DLL supported 90°phase shifter to eliminate the glitches. The proposed DLL supported 90°phase shifter adopted SMIC 65 nm CMOS process with an active area of 0.018 mm2 and the supply voltage of 1.2 V. HSPICE simulation results indicated that the proposed DLL supported 90° phase shifter had an operating frequency ranging from 217 MHz to 1GHz and consumed 2.8 mW at 1 GHz. The peak-to-peak and root-mean-square jitters of 90°phase-shifted clock were 17.77 ps and 5.16 ps respectively when a sine noise of 100 MHz and 30 mV was supplied. In addition, when the phase shifter track the process-voltage-temperature (PVT) variations, the outputted 90°phase-shifted clock effectively avoided glitch issues. |
| Key words: glitch free digitally controlled delay line double data rate delay lock loop phase shifter |
