| 引用本文: | 林敏,史靖炜,丁福建,姜帆,陈潇.用于新型符号的频偏补偿和解调的算法与电路[J].哈尔滨工业大学学报,2024,56(5):121.DOI:10.11918/202201068 |
| LIN Min,SHI Jingwei,DING Fujian,JIANG Fan,CHEN Xiao.Frequency offset compensation and demodulation algorithm and circuit for novel symbol[J].Journal of Harbin Institute of Technology,2024,56(5):121.DOI:10.11918/202201068 |
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| 用于新型符号的频偏补偿和解调的算法与电路 |
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林敏,史靖炜,丁福建,姜帆,陈潇
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(特种光纤与光接入网重点实验室(上海大学),上海 201900)
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| 摘要: |
| 为提高传统脉冲位置调制（pulse position modulation,PPM）符号的频谱效率,提出了一种新型码片内4-PPM符号调制方法,在实现1 Gbit/s通信速率的同时,又大大减少所需频谱资源。可在解调时,该符号调制的误码率性能受到发射端时钟和接收端本地时钟之间的频率偏移的极大影响。针对此问题,又提出了一种在模拟域对该符号进行频偏补偿,并实现符号同步和高速数据解调的算法与电路。该电路系统通过消除接收数据和本地时钟的初始相差、提取两者的频偏信息、周期性改变本地时钟的瞬时相位3步实现频偏补偿,并同时在第3步利用本地时钟对接收数据进行解调。为提高相位插值器（phase interpolator,PI）的线性度,本文将延迟锁定环与PI相结合。在2π的插值范围内,实现插值区间32个,插值步长992个,分辨率2.016 ps,最大差分非线性（differential nonlinearity,DNL）0.183°,最大积分非线性（integral nonlinearity,INL）0.325°。此外,本文提出的相位控制算法有效避免了由电流毛刺所引起的输出相位突变。电路基于UMC 40 nm CMOS RF LP工艺进行设计与仿真。仿真结果表明:本文所提出的算法与电路,在典型工艺角下,将接收数据和本地时钟间的50×10-6频率偏差度降至1.03×10-6,频偏补偿准确度达到97.94%,并实现1 Gbit/s的解调速率。该方法对高速PPM数据同步与解调具有良好的工程应用价值。 |
| 关键词: 脉冲位置调制 码片内脉冲位置调制 符号同步 频偏补偿 数据解调 相位插值器 延迟锁定环 |
| DOI：10.11918/202201068 |
| 分类号:TN432 |
| 文献标识码:A |
| 基金项目:国家重点研发计划(2019YFB2204500) |
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| Frequency offset compensation and demodulation algorithm and circuit for novel symbol |
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LIN Min,SHI Jingwei,DING Fujian,JIANG Fan,CHEN Xiao
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(Key Laboratory of Specialty Fiber Optics and Optical Access Networks (Shanghai University), Shanghai 201900, China)
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| Abstract: |
| For the improvement of the spectral efficiency of traditional pulse position modulation (PPM) symbol, a novel Intra-Chip 4-PPM symbol is proposed, which not only achieves a communication rate of 1 Gbit/s, but also greatly reduces the required spectrum resources. While in demodulation, the bit error rate performance of this modulation symbol is greatly affected by the frequency offset between the transmitter’s clock and the receiver’s clock. To address this issue, an algorithm and a circuit are proposed to compensate for the symbol frequency offset, realize symbol synchronization and enable high-speed data demodulation in the analog domain. The circuit system compensates for the frequency offset by eliminating the initial phase difference between the received data and the local clock, extracting their frequency offset information, and periodically changing the instantaneous phase of the local clock. Meanwhile, the local clock is utilized to demodulate the received data in the third step. In order to improve the linearity of the phase interpolator (PI), a delay-locked loop with the PI is introduced in this paper. Within the interpolation range of 2π, the circuit achieves 32 interpolation intervals, a step size of 992, a resolution of 2.016 ps, the maximum differential nonlinearity (DNL) of 0.183°, and the maximum integral nonlinearity (INL) of 0.325°. In addition, the phase control algorithm proposed in this paper effectively avoids the output phase jump caused by current glitch. Based on UMC 40 nm CMOS RF LP process, simulation results show that the proposed algorithm and circuit reduce the frequency deviation between received data and local clock from 50×10-6to 1.03×10-6 and the accuracy of frequency offset compensation reach 97.94% in the typical corner, enabling a demodulation rate of 1 Gbit/s. This method has significant engineering application value for synchronization and demodulation of high-speed PPM data. |
| Key words: pulse position modulation Intra-Chip pulse position modulation symbol synchronization frequency offset compensation data demodulation phase interpolator delay-locked loop |
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